In general, when data communication is performed via a transmission line or the like having a large transmission loss, an equalization circuit is used on the receiver side so as to compensate the transmission loss. FIGS. 11A and 11B illustrate an example of an equalization circuit. The equalization circuit EQ illustrated in FIG. 11A includes transistors T1 to T8, resistance elements R1 to R4 and a capacitance element C1. The transistors T1, T2 (T3, T4) are coupled in series between an output terminal OUT (OUTX) and a ground line. A control terminal of the transistor T1 (T3) is coupled to an input terminal INX (IN). Control terminals of the transistors T2, T4 are coupled to a bias terminal BIAS. The resistance element R1 and the capacitance element C1 are coupled in parallel between a connection node of the transistors T1, T2 and a connection node of the transistors T3, T4. The resistance element R1 is a variable resistance element in which a resistance value changes corresponding to an equalization coefficient value of the equalization circuit EQ.
The transistors T5, T6 (T7, T8) are coupled in series between a connection node of the transistor T1 (T3) and the output terminal OUT (OUTX) and a ground line. A control terminal of the transistor T5 (T7) is coupled to the connection node of the transistor T1 (T3) and the output terminal OUT (OUTX). Control terminals of the transistors T6, T8 are coupled to the bias terminal BIAS. The resistance R2 is coupled between a connection node of the transistors T5, T6 and a connection node of the transistors T7, T8. The resistance R3 (R4) is coupled between the connection node of the transistor T1 (T3) and the output terminal OUT (OUTX) and a power supply line.
The equalization circuit EQ having such a structure allows adjusting the resistance value of the resistance element R1 via the equalization coefficient value so as to change a gain-frequency characteristic. For example, when the equalization coefficient value of the equalization circuit EQ is changed in eight steps (c0=0x0, c1=0x1, . . . , c7=0x7), the gain-frequency characteristic of the equalization circuit EQ changes as illustrated in FIG. 11B. As can be understood from FIG. 11B, the equalization circuit has a function to amplify a high frequency component of an input signal. In a receiver circuit receiving an output signal of a transmitter circuit via a transmission line, an input signal in the receiver circuit has an attenuated high frequency component, and thus the equalization circuit is used for compensating the attenuated high frequency component. The waveform (eye pattern) of an input signal of the receiver circuit changes due to temperature changes and changes over time of the transmission line, and thus it may be necessary to adjust the equalization coefficient value of the equalization circuit in accordance with characteristics of the transmission line, so as to assure an amplitude that is adequate for allowing decision with respect to an input signal of a data decision circuit provided in a latter stage of the equalization circuit. A technique to realize the operations described above is adaptive equalization.
FIG. 12 illustrates the concept of adaptive equalization. When the waveform of an input signal in a receiver circuit 520 changes accompanying a temperature change in a transmission line 500 provided between a transmitter circuit 510 and the receiver circuit 520, for example when a loss of the transmission line 500 becomes large and the amplitude of an input signal in the receiver circuit 520 becomes small, the equalization coefficient value of an equalization circuit 521 is adjusted by the adaptive equalization, so as to assure an amplitude that is adequate for allowing decision with respect to an input signal of a data decision circuit 522. Thus, the adaptive equalization is a technique to detect the influence of temperature changes and changes over time of a transmission line or the like on an input signal of a receiver circuit, and adjust the equalization coefficient value of an equalization circuit according to the degree of the influence. When data communication is performed via a transmission line having a large transmission loss or the like, for example when data communication is performed via a cheaper transmission line, the adaptive equalization is an indispensable technique.
FIG. 13 illustrates an example of a receiver circuit. A receiver circuit 12 receiving an output signal of a transmitter circuit 111 via a transmission line 10 includes an equalization circuit 13, a data decision circuit 14, a demultiplexer (DEMUX) 15, an analog-to-digital converter (ADC) 16, and an adaptive equalization control circuit 17. The adaptive equalization control circuit 17 includes a selector (SEL) 18, an amplifier (AMP) 19, a subtractor 20, a step size parameter circuit (SSP) 21, and an integrator 22. Note that the receiver circuit illustrated in FIG. 13 is equivalent to one disclosed in Non-patent Document 1, and thus detailed descriptions of respective circuits will be omitted.
In the receiver circuit of the type illustrated in FIG. 13, the adaptive equalization control circuit employs a method to adjust the equalization coefficient value of the equalization circuit based on an algorithm using a least squares method. In the method described above, the difference between an output amplitude y of the equalization circuit and an expected amplitude d is obtained as an amplitude error e, and feedback control with respect to the equalization circuit is performed so that the mean square value of the amplitude error e becomes small. Further, when making an LSI of the adaptive equalization control circuit, generally the adaptive equalization control circuit is realized in a digital area having high affinity with LSIs. Therefore, in the receiver circuit 12, there is provided an analog-to-digital converter 16 converting an output amplitude of the equalization circuit 13 into a digital value. Further, when obtaining an expected value for the output value of the analog-to-digital converter 16, it is just needed to multiply the output logical value (“+1” or “−1”) of the data decision circuit 14 by an expected amplitude. However, there exists an input-output latency in the analog-to-digital converter 16, and thus it may be necessary to obtain the logical value corresponding to output data of the analog-to-digital converter 16 from output data of the demultiplexer 15. Accordingly, in the adaptive equalization control circuit 17, the one bit data corresponding to the output data of the analog-to-digital converter 16 is selected by the selector 18 from plural bit data output from the demultiplexer 15. However, when making the LSI of the adaptive equalization control circuit, the timing adjustment described above leads to increases in circuit scale and power consumption.
FIG. 14 illustrates another example of a receiver circuit. The receiver circuit illustrated in FIG. 14 includes an equalization circuit (EQ) 30, a data decision circuit 32, a boundary decision circuit 33, a demultiplexer (DEMUX) 34, a clock recovery unit (CRU) 36, an equalization parameter control unit (EQ parameter control unit) 38, a clock generation circuit (PI) 40, and an inter-symbol interference monitor unit (ISI monitor unit) 52. Note that the receiver circuit illustrated in FIG. 14 is equivalent to one disclosed in Patent Document 1, and thus detailed descriptions of respective circuits will be omitted.
In the receiver circuit illustrated in FIG. 14, the inter-symbol interference monitor unit 52 and the equalization parameter control unit 38 play the main role of the adaptive equalization function. When deriving an optimal value of an equalization parameter EQPR of the equalization circuit 30, an output signal Dn of the data decision circuit 32 and an output signal Dn(b) of the boundary decision circuit 33 are used. In the clock generation circuit 40, the phase of a clock signal DBT that defines a decision timing in the boundary decision circuit 33 changes dynamically according to a delay amount control code DELAY supplied from the equalization parameter control unit 38. In the inter-symbol interference monitor unit 52, a phase fluctuation amount of an output signal An of the equalization circuit 30 is detected based on the logical comparison result between the output signal Dn of the data decision circuit 32 and the output signal Dn(b) of the boundary decision circuit 33. In the equalization parameter control unit 38, the value of the equalization parameter EQPR is adjusted so that the phase fluctuation amount detected by the inter-symbol interference monitor unit 52 becomes small. In the receiver circuit illustrated in FIG. 14, the adaptive equalization function is realized by such a series of operations.
However, a point that has to be noted here is that the output signal Dn of the data decision circuit 32 and the output signal Dn(b) of the boundary decision circuit 33 are used not only for the adaptive equalization function but for a CDR (Clock and Data Recovery) function. To dynamically change the phase of the clock signal DBT for the boundary decision circuit 33 is nothing but to generate noise internally, but when the phase of the clock signal DBT is changed at a speed equal to or higher than the bandwidth of the CDR function, this noise is removed by the CDR function. However, the convergence time of the equalization parameter EQPR to the optimal value by the adaptive equalization function may be adequately long, and in such a situation, changing the phase of the clock signal DBT at a high speed leads to increase in power consumption of the receiver circuit. Therefore, it is hard to say that the receiver circuit illustrated in FIG. 14 has a highly realizable structure.
Patent Document 1 Japanese Laid-open Patent Publication No. 2005-303607
Non-patent Document 1: Jan W. M. Bergmans, “Digital Baseband Transmission and Recording”, Kluwer Academic Publishers, pp. 373-450, 1996
As a device for realizing adaptive equalization, one that performs feedback control for the equalization circuit based on information related to the amplitude of an output signal of an equalization circuit, as in the receiver circuit illustrated in FIG. 13, is generally used. However, problems such as increase in circuit scale and power consumption arise when making the LSI of the adaptive equalization control circuit, and thus a much simpler realization device is demanded. As a realization device responding to this demand, one that performs feedback control for the equalization circuit based on information related to the phase of an output signal of the equalization circuit, as in the receiver circuit illustrated in FIG. 14, is effective. However, the circuit structure for realizing the adaptive equalization function works in a manner to reduce the CDR function, and thus it is difficult to establish both the CDR function and the adaptive equalization function.